1. Field of the Invention
This invention relates to semiconductor device manufacturing, and more particularly, to an improved method for processing a semiconductor topography.
2. Description of the Related Art
The following descriptions and examples are not admitted to be prior art by virtue of their inclusion within this section.
Forming substantially planar surfaces during the processing of a semiconductor topography may involve numerous fabrication steps. For example, a layer may be formed across a previously patterned layer of a semiconductor topography using a process such as chemical vapor deposition (“CVD”). Elevational disparities of the deposited layer may be reduced by planarizing the layer using a process such as chemical mechanical polishing (“CMP”). Alternatively, an opening or a trench may be formed within a semiconductor topography and subsequently filled with a layer of trench fill material. In this manner, the layer of trench fill material may be formed within the opening and on an upper surface of the semiconductor surface. The layer of trench fill material may then be planarized such that an upper surface of the structure within the trench may be substantially planar with an upper surface of the semiconductor topography.
Substantially planar surfaces within a semiconductor topography may play an important role in the functionality of a semiconductor device. For example, step coverage problems may arise when a dielectric, conductive, or semiconductive material is deposited over a surface having raised and recessed regions. Step coverage is defined as a measure of how well a film conforms over an underlying step and is expressed by the ratio of the minimum thickness of a film as it crosses a step to the nominal thickness of the film over horizontal regions. Furthermore, substantially planar surfaces may become increasingly important as the feature sizes of semiconductor devices are reduced, since the depth of focus required to pattern an upper surface of a topography may increase with reductions in feature size. If a topography is nonplanar, the patterned image may be distorted and the intended structure may not be formed to the specifications of the device. Furthermore, correctly patterning layers upon a surface containing fluctuations in elevation may be difficult using optical lithography. The depth-of-focus of the lithography alignment system may vary depending upon whether the resist resides in an elevational “hill” or “valley” area.
As mentioned above, CMP is a technique that may be employed to planarize or remove the elevational fluctuations in the surface of a semiconductor topography. A conventional CMP process may involve placing a semiconductor wafer face-down on a polishing pad which lies on or is attached to a table or platen. During the CMP process, the polishing pad and/or the semiconductor wafer may be set into motion as the wafer is forced against the pad. For example, the polishing pad and the wafer may be placed on rotatable tables such that the wafer and the polishing pad may be rotated relative to each other. Alternatively, the wafer may be rotated relative to a fixed pad or vice versa. In another embodiment, the polishing pad may be a belt, which traverses against a fixed or rotating wafer. An abrasive, fluid-based chemical suspension, often referred to as a “slurry,” may be deposited onto the surface of the polishing pad. The slurry fills the space between the polishing pad and the wafer surface such that a chemical in the slurry may react with the surface material being polished. The rotational movement of the polishing pad relative to the wafer causes abrasive particles entrained within the slurry to physically strip the reacted surface material from the wafer. Therefore, the process may employ a combination of chemical stripping and mechanical polishing to form a planarized surface.
Unfortunately, a CMP process may not form a substantially planar surface across the entire semiconductor topography. For instance, the slurry may react in recessed regions, causing those regions to be excessively etched. Furthermore, the polishing rate of the CMP may be dependent upon the polish characteristics of the topography. As a result, the polishing pad, being somewhat conformal to the surface topography, may deform in response to polishing laterally adjacent layers comprising different polish properties. Therefore, while the removal rate of raised regions of the dielectric may be greater than that of the recessed regions, a significant amount of the recessed regions may, unfortunately, undergo removal. This phenomena is known as the “dishing” effect and may reduce the degree of planarization that can be achieved by the CMP process. Consequently, the “dishing” effect may cause upper surfaces of structures and layers to curve below polished upper surfaces of adjacent structures or layers. For example, relatively shallow trench isolation regions are typically formed within a semiconductor substrate to isolate impurity regions of active devices placed in the substrate. The dishing effect may be so severe that some portions of the upper surface of the shallow trench isolation regions may extend below the upper surface of the substrate by approximately 500 angstroms. As a result, the active regions of the device may not be adequately isolated.
To insure that the upper surfaces of isolation regions are above or coplanar with upper surfaces of adjacent active regions, a polish stop layer may be used to terminate the polishing process at an elevation above the semiconductor substrate. The composition of the polish stop layer is such that it polishes much more slowly than the layer above it. In this manner, polishing may be substantially terminated upon exposing the polish stop layer. Thus, layers or structures formed upon the semiconductor topography adjacent to the polish stop layer may also be polished to approximately the same elevation level as the polish stop layer. Silicon nitride is typically used as a polish stop layer since it is a relatively hard material, particularly compared to silicon dioxide.
As such, a technique with which to form shallow trench isolation regions may include depositing a layer of silicon nitride (“nitride”) across an upper surface of a semiconductor substrate. A “pad” oxide layer is typically interposed between the substrate and nitride layer to reduce inherent stresses between nitride and silicon. Portions of the nitride layer and substrate are etched away to define a trench within the substrate. Fill oxide (i.e., silicon dioxide) is then deposited into the trench to a level spaced above the upper surface of the nitride layer. The resulting upper surface of the fill oxide includes a recessed region elevationally raised above the trench area. A trench isolation region may then be formed by subjecting the semiconductor topography to a CMP process. The polish rate of the nitride layer is so slow that the nitride layer acts as a polish stop layer. Subsequent to the CMP process, the nitride layer may be removed by a nitride strip followed by a selective etch technique to remove the pad oxide.
A disadvantage of the polish stop process described above is a problem known as the “dishing effect”. During the CMP process, the slurry, being a relatively viscous fluid, may flow to the recessed region of the fill oxide. Further, the polishing pad, being somewhat conformal to the semiconductor topography, may deform above the recessed region in response to the polishing characteristic differences between the fill oxide and nitride layer. Consequently, the fill material may be undesirably “dug out” of some trenches and thus, the “dishing effect” may be observed. The “dishing effect” may be further augmented by “overpolishing” the polish stop layer. It is important to remove all fill oxide above the nitride layer for subsequent removal of the polish stop layer. Therefore, the surface may be “overpolished” or polished to a level spaced below the original upper surface of the nitride layer to ensure that the fill oxide no longer resides above the nitride layer. Furthermore, the dishing effect may be dependent on pattern density. For example, a pattern having relatively few and/or relatively narrow isolation trenches may include a large amount of nitride across the lateral portion of the topography, which results in a slower polish rate. Alternatively, patterns having relatively many and/or wide isolation trenches may include less nitride across the lateral surface of the semiconductor topography, resulting in a faster polish rate and a thicker amount of nitride needed to compensate for the increase in the polish rate.
It is, therefore, advantageous to form a polish stop layer having a sufficient thickness such that the “dishing effect” does not extend below the upper most surface of the substrate subsequent to polishing. Typically, the thickness of the polish stop layer may be greater than 500 angstroms and possibly greater than 1000 angstroms. Unfortunately, the use of a relatively thick polish stop layer may create a significant step height between the resulting shallow trench isolation region and adjacent regions upon removal of the polish stop layer. The “step height” as used herein refers to the upper portion of the shallow trench isolation region that extends above the upper surface of adjacent regions. Such a step height may have a thickness between approximately 500 angstroms and approximately 2000 angstroms. Unfortunately, this step height may be significant enough to cause the aforementioned problems associated with non-planar surfaces. In addition, incomplete removal of subsequently deposited polysilicon at step edges may result in the formation of “poly stringers” in subsequent processing, which may adversely affect the performance of the circuit. Furthermore, since the nitride layer increases the depth of the trench which must be filled by the fill oxide, a thicker fill oxide is needed. Such a formation of a relatively thick fill oxide above the nitride layer can be rather time-consuming and costly.
Accordingly, it would be advantageous to develop a method for forming a semiconductor topography having a substantially planar upper surface across the entire semiconductor topography. In particular, it would advantageous to reduce the thickness of or eliminate a polish stop layer for the formation of a substantially planar surface.